1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a DRAM (dynamic random access memory) composed of open-bit-line type capacitor-over-bit-line (COB) structure memory cells.
2. Description of Related Art
A DRAM composed of one-transistor one-capacitor memory cells has increased its storage capacity by four times every three years (alternation of generations) due to advancement in micro-fabrication technology, device technology and circuit technology. In addition, the memory cell size has been reduced to about 40% of the memory cell of the preceding generation. With the reduction of the memory cell size, it is necessary to correspondingly reduce the size of various elements constituting the memory cell, and actually, the transistor has been reduced in size in accordance with a so called scaling rule. However, in order to ensure a satisfactory S/N ratio and a higher immunity to soft error, the capacitor of each DRAM memory cell is required to have a storage capacitance of not smaller than a certain constant value. Therefore, it is not allowed to reduce the storage capacitance in proportion with the reduction of the memory cell area in a plan view. This is a large problem.
In order to obtain a large storage capacitance even if the capacitor area is reduced in a plan view projected on a principal surface of a semiconductor substrate, a stacked capacitor has been already reduced in practice, in which a storage node electrode constituting a lower plate of the capacitor is constructed in a three-dimensional structure, namely, to have a substantial height, and a side surface of the storage node electrode is effectively utilized. The initially proposed memory cell using the stacked capacitor was so constructed that the capacitor is formed above the transistor and a bit line is formed over the capacitor.
However, this structure has the following two problems: First, if the height of the storage node is elevated to increase a side surface area for the purpose of increasing the storage capacitance, the depth of a contact hole for interconnecting between a bit line and one of a pair of source/drain diffused regions of the associated transistor (bit contact hole) becomes large, with the result that it becomes difficult to form the contact hole. In addition, since a step difference in an insulator film covering the capacitor becomes large, it also becomes difficult to form the bit line. Secondly, the area of the capacitor projected in the plan view, used within the memory cell area, inevitably becomes small by the area of the bit line contact.
In order to overcome the above mentioned problems, T. Ema et al, "3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMs", 1988 International Electron Devices Meeting Technical Digest, pages 592-595, reported the so called COB structure memory cell in which the capacitor is formed over the bit line. In this report, a T-shaped device formation region is confined on a surface of the semiconductor substrate, and a bit line is connected through a bit contact hole to one of a pair of source/drain diffused regions, formed in a center bar portion of the T-shaped device formation region, and over the bit line there is formed a capacitor which is connected through a capacitor contact hole to the other of the pair of source/drain diffused regions, positioned at one of opposite ends of the T-shaped device formation region. The memory cell of the structure proposed in this report is disadvantageous in that a junction capacitance in the one source/drain diffused region connected to the bit line becomes large, so that a parasite capacitance of the bit line correspondingly becomes large.
Japanese Patent Application Pre-examination Publication No. JP-A-03-072673 and its corresponding U.S. Pat. No. 5,172,202, (the content of which is incorporated by reference in its entirety into this application) proposed to reduce the parasite capacitance of the bit line by providing a local interconnection.
Now, the first prior art semiconductor memory disclosed by JP-A-03-072673 and U.S. Pat. No. 5,172,202, will be described with reference to FIGS. 1A, 1B and 1C and FIGS. 2A and 2B. FIGS. 1A, 1B and 1C are layout diagrams at different levels, and FIG. 1A illustrates a positional relation between a device formation region, a word line and a local interconnection. FIG. 1B illustrates a positional relation between the local interconnection and a bit line, and FIG. 1C illustrates a positional relation between the bit line and a capacitor storage node (capacitor lower plate). FIG. 2A is a sectional view taken along the line A--A in FIGS. 1A, 1B and 1C, and FIG. 2B is a sectional view taken along the line B--B in FIGS. 1A, 1B and 1C.
A field oxide film 402 is formed in a device isolation region on a principal surface of a P-type silicon substrate 401, so that a number of rectangular device formation regions 403A confined by the field oxide film 402 are formed on the principal surface of the P-type silicon substrate 401. The rectangular device formation regions 403A are arranged to form a plurality of rectangular device formation region arrays extending along a long side of each rectangular device formation region 403A, and two adjacent rectangular device formation regions included in two different but adjacent rectangular device formation region arrays, respectively, are staggered by one half of a pitch of the rectangular device formation region in a direction along the long side of each rectangular device formation region 403A. In each rectangular device formation region 403A, two transistors are formed.
In each rectangular device formation region 403A, a gate oxide film 404 is formed on the principal surface of the P-type silicon substrate 401, and two word lines 405A each acting as a gate electrode are formed on the gate oxide film 404. Each word line 405A extends generally orthgonally to the long side of each rectangular device formation region 403A, while depicting a slight zigzag line. In addition, in each rectangular device formation region 403A, one N-type diffused layer 406A and two N-type diffused layers 406B are formed in self alignment with the word lines 405A and the field oxide film 402.
A local interconnection 409A connected through a local contact hole 408A to a corresponding N-type diffused layer 406B, extends to pass over the word line 405A adjacent to the rectangular device formation region 403A, and then to reach the field oxide film 402. Two local interconnections 409A connected to the two N-type diffused layers 406B, respectively, formed in each one rectangular device formation region 403A, extend in an opposite direction to each other, at a desired angle to the long side of each rectangular device formation region 403A.
A bit line 413A connected to the N-type diffused layer 406A through a bit contact hole 411A (which is filed with a contact plug 412), is formed at a level higher than those of the word lines 405A and the local interconnection 409A, and is located to extend along the rectangular device formation region array 403A. Furthermore, a capacitor storage node 417 (constituting a capacitor lower plate) connected to a corresponding local interconnection 409A through a capacitor contact hole 415 which is positioned for example above the field oxide film 402 and which reaches one end of the corresponding local interconnection 409A, is formed at a level higher than those of the word lines 405A and the bit lines 413A. A surface of the capacitor storage node 417 is coated with a capacitor dielectric film (not shown) and further covered with a cell plate 419 (constituting a capacitor upper plate).
Another prior art memory cell using the local interconnection was disclosed by Japanese Patent Application Pre-examination Publication No. JP-A-04-279055 (an English abstract of which is available from the Japanese Patent Office, and the content of the English abstract of JP-A-04-279055 is incorporated by reference in its entirety into this application). This second prior art memory cell will be described with reference to FIG. 3, which is a plan view illustrating a layout pattern of the second prior art memory cell, with the bit line being partially removed out for showing a layout structure under the bit line.
Rectangular device formation regions 403B confined on a principal surface of a semiconductor device are arranged to form a plurality of rectangular device formation region arrays extending along a long side of each rectangular device formation region 403B, and two adjacent rectangular device formation regions included in two different but adjacent rectangular device formation region arrays, respectively, are staggered by one half of a pitch of the rectangular device formation region in a direction along the long side of each rectangular device formation region 403A. In each rectangular device formation region 403A, two transistors are formed. On a gate oxide film formed inn each rectangular device formation region 403A, two word lines 405B each acting as a gate electrode are formed, each of which extends generally orthgonally to the long side of each rectangular device formation region 403B.
Differently from the local interconnection in the first prior art memory cell disclosed in JP-A-03-072673 and U.S. Pat. No. 5,172,202, a local interconnection 409B of this second prior art memory cell is connected through a local contact hole 408B to a diffused layer formed in the rectangular device formation region 403B between the two word lines 405B. The local interconnection 409B extends over the device formation region 403B, in parallel to the word line 405B. A bit line 413B connected through a bit contact hole 411B to a portion of the local interconnection 409B extending over a device isolation region which confines the rectangular device formation regions 403B, is formed in parallel to the device formation region arrays. Opposite end portions 424 of each rectangular device formation region 403B, which do not overlap the bit line 413B, are connected to corresponding capacitors (not shown), respectively.
Here, the cell size of the DRAM memory cell is expressed by F (Feature-size) which is defined as being one half of the pitch of the word line. On the other hand, the DRAM memory cell disclosed in JP-A-03-072673 and U.S. Pat. No. 5,172,202, is of a turned-back bit line type, and the DRAM memory cell disclosed in JP-A-04-279055 is of an open-bit-line type. In the prior art DRAM memory cell disclosed in JP-A-03-072673 and U.S. Pat. No. 5,172,202, by adopting the rectangular device formation regions and the local interconnections, the pitch of the rectangular device formation regions is 8 F in a bit line direction (along the long side of the rectangular device formation regions) and 2 F in a word line direction. Therefore, the cell size of the memory cell of the turned-back bit line type the DRAM memory cell disclosed in JP-A-03-072673 and U.S. Pat. No. 5,172,202 can be reduced to 8 F.sup.2 which is a target value in this type memory cell. However, this value is larger, by 2 F.sup.2, than 6 F.sup.2 which is a target value in the open-bit-line type DRAM memory cell as disclosed in JP-A-04-279055.
The open-bit-line type memory cell is advantageous over the turned-back bit line type memory cell in that the cell size can be reduced in comparison with the turned-back bit line type memory cell. In the open-bit-line type memory cell, the pitch of device formation regions (in each of which two memory cells are formed) is 6 F in the bit line direction. Therefore, if the pitch of the memory cells in the word line direction can be made to 2 F, the memory cell size can be made to 6 F.sup.2. In a cell array composed of conventional open-bit-line type memory cells having the device formation regions located with the bit line direction pitch of 6 F, no stagger exists between two adjacent device formation regions which are included in different but adjacent device formation region arrays, and therefore, the spacing between two word lines passing over two adjacent device formation regions included in the same device formation region array, becomes 3 F, and an empty device formation region exists between these word lines and in parallel to these word lines.
Because of this reason, even if the rectangular device formation regions and the local interconnections as disclosed in JP-A-03-072673 and U.S. Pat. No. 5,172,202 or JP-A-04-279055 are adopted, since it is necessary to take into consideration a spacing (=F) between local interconnections, the pitch of the memory cell in the word line direction becomes 3 F (not 2 F) similarly to the open-bit-line type memory cell having the T-shaped device formation region, with the result that the cell size of the memory cell becomes 9 F.sup.2 which is greatly larger than 6 F.sup.2 which the target value in the open-bit-line type memory cell. Because of the above mentioned circumstance, the DRAM composed of the open-bit-line type memory cells has not adopted the means proposed by JP-A-03-072673 and U.S. Pat. No. 5,172,202 or JP-A-04-279055, and various efforts and studies are being made to approach the word line direction pitch of the memory cells to 2 F. However, this has not yet been realized.